For the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aide in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist which is specific to a particular vendor's technology/architecture.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floor planning.” A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and the routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
Controlling timing problems is an important aspect of designing a digital circuit. At various stages of a design process (e.g, synthesis, placement, routing, floor planning, partitioning, optimization, and others), timing analyses are performed to budget and/or verify timing. For example, after placement of components on the chip and routing of wires between components, timing analysis (e.g., timing simulation, or static timing analysis) can be performed to accurately determine the signal delays between logic elements in order to determine whether or not timing requirements are satisfied. In the floor planning operation, timing analysis can be performed to budget delays. Some transformations (e.g., from the HDL code to an RTL netlist, from a technology independent RTL netlist to a technology specific netlist, optimization, and others) are timing driven.
One parameter for describing timing requirements is slack. Slack is the difference between the desired delay and the actual (estimated or computed) delay. When the desired delay is larger than the actual delay, the slack is positive; otherwise, the slack is negative. Typically, it is necessary to make the slack positive (or close to zero) to meet the timing requirement.
Time Division Multiplexing (TDM) channels have been used in digital circuits to allow multiple connections to share one or more physical wires in transmitting signals between chips and circuit boards. The presence of TDM channels in a digital circuit greatly increases the complexity of timing analyses.
An electronic system involving transmission of data typically uses at least one physical communication links (e.g., wires) between the sender and the receiver. Examples of communication links include: computer networks, telephone networks, a cable connecting a computer and a printer, traces on a printed circuit board that connect the chips on the board, and others.
As systems grow more complex and more data needs to be transmitted, more physical connections may be used to transfer the data. However, the cost of the physical communication links is one of the important factors that determine the cost of the system. Time Division Multiplexing (TDM) is one of the techniques for reducing the amount of required physical communication links.
Typically, on the sending side of a TDM channel, the signals from different connections are stored into a sender queue. The stored signals are sequentially sent one signal at a time over a shared physical communication link of the TDM channel. On the receiving side, signals are received in the order they are sent and stored in the receiver queue. After the signals for all the different connections are sent sequentially from the sender queue through the TDM channel to the receiver queue, a next cycle is repeated to send more signals for the connections. Thus, the TDM channel provides a shared communication channel, in which signals for all the connections are sent in different time slots in a cycle using the shared physical communication link. Some TDM channels use more than one physical communication link; and, some TDM channels encode multiple signals to send them through more than one physical wire.
A TDM channel typically operates according to its own clock signal. The TDM scheme is synchronous when the TDM clock and the system clock are synchronized; and, it is asynchronous when they are not. The presence of a TDM channel, especially an asynchronous TDM channel, greatly increases the complexity of timing analysis, because of the complex logic of the TDM channel and the addition of the clock domain for the TDM channel. The signal on the sender side belongs to the system clock domain. It is transferred to the TDM clock domain for transmission in the TDM channel and then to the system clock domain on the receiver side. Additional difficulty is posed by the asynchronicity of the TDM clock domain in an asynchronous TDM channel.